[aarch64-port-dev ] RFR: 88158361: AArch64: Address calculation missed optimizations

[Zhongwei Yao]

Hi, Andrew,

On 16 June 2017 at 16:36, Andrew Haley <aph at redhat.com> wrote:

> On 16/06/17 05:40, Zhongwei Yao wrote:
> > By the way, the counterpart sub extension rule (like SubExtL_sxtw_imm) is
> > also missing. And moreover, other add/sub extension rules (like
> > AddExtL_uxtb_and_shift, AddExtL_uxth_and_shift etc.) are also missing.
> But
> > these rules are not hit at all in my real world benchmark tests. I feel
> > they are too specific to be matched. So I do not include them in my
> patch.
>
> It looks like these are cases which are missing from the patterns
> generated by the macros in aarch64_ad.m4.  It would be better if you
> added them all there.
>

Yeah, they are missing in aarch64_ad.m4.

And there are 32 kinds of add/sub extension combination. I have tried to
add 18 rules in aarch64.ad, and found many of them are quite contrived,
like:
    subw  $dst, $src1, $src2, uxtb, #lshift //match rule: Set dst (SubI
src1 (LShiftI (AndI src2 mask) lshift)), where mask=255. java code: z = x -
((y & 255) << lshift), where x, y, z are all int, lshift = [0, 4]
    addw  $dst, $src1, $src2, uxth, #lshift //match rule: Set dst (AddI
src1 (LShiftI (AndI src2 mask) lshift)), where mask=65535. java code: z = x
+ ((y & 65535) << lshift), where x, y, z are all int, lshift = [0, 4]

Shall I add all of these 18 rules?

And for the left 14 combination (as following), I have not come up rules to
utilise such instructions. Do you have any suggestion?
    add SXTB (simplified for add rd, rm, rn, sxtb, #[0,4], same for below)
    add SXTH
    add SXTX
    addw SXTB
    addw SXTH
    addw SXTW
    addw SXTX
    sub SXTB
    sub SXTH
    sub SXTX
    subw SXTB
    subw SXTH
    subw SXTW
    subw SXTX

--
Thanks!


>
> Thanks.
>
> --
> Andrew Haley
> Java Platform Lead Engineer
> Red Hat UK Ltd. <https://www.redhat.com>
> EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671
>



-- 
Best regards,
Zhongwei