[aarch64-port-dev ] RFR(S): 8214922: Add vectorization support for fmin/fmax

[Andrew Haley]

Hi Roland,

I'm looking at the test code and I can't figure out why trivial reduction doesn't
seem to be working. In fact, I can't even get this to work:

    @Benchmark
    public float testPlusReduceFloat(BenchmarkState state) {
        float[] fa = state.fa;
        float sum = 0;
        for (int i = 0; i < fa.length; i++) {
            sum += fa[i];
        }
        return sum;
    }

Should this work? And if not, do you have any idea of what code I could use to
test the SIMD reduction?

-- 
Andrew Haley
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
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