[aarch64-port-dev ] RFR(S): 8214922: Add vectorization support for fmin/fmax

[Vladimir Ivanov]

Andrew,

Haven't checked AArch64, bu there's some logic to enable reduction 
vectorization only for more complex code shapes (see [1] for some details).

I was able to trigger auto-vectorization on x86 for the following code 
shape:
     int r = 0;
     for (int i = 0; i < MAX; i++) {
         r += A[i]*B[i];
     }

Best regards,
Vladimir Ivanov

[1] https://bugs.openjdk.java.net/browse/JDK-8078563

On 21/12/2018 09:02, Andrew Haley wrote:
> Hi Roland,
> 
> I'm looking at the test code and I can't figure out why trivial reduction doesn't
> seem to be working. In fact, I can't even get this to work:
> 
>      @Benchmark
>      public float testPlusReduceFloat(BenchmarkState state) {
>          float[] fa = state.fa;
>          float sum = 0;
>          for (int i = 0; i < fa.length; i++) {
>              sum += fa[i];
>          }
>          return sum;
>      }
> 
> Should this work? And if not, do you have any idea of what code I could use to
> test the SIMD reduction?
>