[aarch64-port-dev ] RFR(S): 8204353 - AARCH64: optimize FPU load and stores in macroAssembler

[Andrew Haley]

On 06/06/2018 01:30 PM, Dmitrij Pochepko wrote:
> You can take a look here: 
> http://hg.openjdk.java.net/jdk/jdk/file/tip/src/hotspot/cpu/aarch64/assembler_aarch64.hpp#l2068
> As you can see, switch by a.getMode() has 3 cases:
> 
> 1) "base_plus_offset" (expecting only 0 offset. This is for "base 
> register, no offset" ld/st addressing mode
> 2) "post"- this if for immediate post-index mode
> 3) "base_plus_offset_reg" which is treated further as register 
> post-index mode.

Well, yes, but I can't see that being [ab]used anywhere in the existing
source.

> I'll create separate issue and patch, which will add new address mode 
> (something like: "post_reg"). And final syntax for such mode usage will 
> be ... Address(post(<reg1>, <reg2>)), which makes it more readable. 

Yes.  And please disallow the use of Address(reg, reg) while you're doing
that.

> After that I'll update this fpu ld/st optimization patch accordingly.

OK.

-- 
Andrew Haley
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671