[aarch64-port-dev ] RFR(S): 8204353 - AARCH64: optimize FPU load and stores in macroAssembler

[Dmitrij Pochepko]

On 06.06.2018 15:37, Andrew Haley wrote:
> On 06/06/2018 01:30 PM, Dmitrij Pochepko wrote:
>> You can take a look here:
>> http://hg.openjdk.java.net/jdk/jdk/file/tip/src/hotspot/cpu/aarch64/assembler_aarch64.hpp#l2068
>> As you can see, switch by a.getMode() has 3 cases:
>>
>> 1) "base_plus_offset" (expecting only 0 offset. This is for "base
>> register, no offset" ld/st addressing mode
>> 2) "post"- this if for immediate post-index mode
>> 3) "base_plus_offset_reg" which is treated further as register
>> post-index mode.
> Well, yes, but I can't see that being [ab]used anywhere in the existing
> source.
>
>> I'll create separate issue and patch, which will add new address mode
>> (something like: "post_reg"). And final syntax for such mode usage will
>> be ... Address(post(<reg1>, <reg2>)), which makes it more readable.
> Yes.  And please disallow the use of Address(reg, reg) while you're doing
> that.
>
>> After that I'll update this fpu ld/st optimization patch accordingly.
> OK.
>

Please take a look at webrev.02: 
http://cr.openjdk.java.net/~dpochepk/8204353/webrev.02/

The only change is to match changes in JDK-8204473 -  AARCH64: register 
post-index addressing mode is not supported directly

2 entries of "Address(sp, rscratch1)" is now "Address(post(sp, rscratch1))"


I relaunched hotspot jtreg compiler tests as sanity with both patches. 
No new failures found.


Thanks,

Dmitrij