RFR: 8199138: Add RISC-V support to Zero

[David Holmes]

This seems fine to me too.

Thanks,
David

On 13/02/2020 3:08 am, John Paul Adrian Glaubitz wrote:
> Hi!
> 
> On 2/12/20 5:51 PM, Aleksey Shipilev wrote:
>> Neat. Looks good to me.
>>
>> Minor nits in os_linux.cpp:
>>
>> *) Can you move the comment to the #define line, as it is done in the similar blocks in the same file?
>>
>> 1854 #ifndef EM_RISCV                          /* RISCV */
>> 1855   #define EM_RISCV      243
>> 1856 #endif
>>
>> *) I believe this one is sorted alphabetically, so RISCV should be between __powerpc64__ and S390?
>>
>> -        AARCH64, ALPHA, ARM, AMD64, IA32, IA64, M68K, MIPS, MIPSEL, PARISC, __powerpc__,
>> __powerpc64__, S390, SH, __sparc
>> +        AARCH64, ALPHA, ARM, AMD64, IA32, IA64, M68K, MIPS, MIPSEL, PARISC, __powerpc__,
>> __powerpc64__, S390, SH, __sparc, RISCV
> 
> I have done that now. Updated RFR in [1].
> 
> Adrian
> 
>> [1] http://cr.openjdk.java.net/~glaubitz/8199138/webrev.01/
>