/hg/icedtea7-forest/hotspot: 4 new changesets
adinn at icedtea.classpath.org
adinn at icedtea.classpath.org
Tue Feb 3 11:50:52 UTC 2015
changeset 91ad61609a7a in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=91ad61609a7a
author: aph
date: Fri Dec 19 06:31:51 2014 -0500
Remove insanely large stack allocation in entry frame.
changeset ec4c8090b073 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=ec4c8090b073
author: aph
date: Fri Jan 02 05:38:12 2015 -0500
Fix implementation of InterpreterMacroAssembler::increment_mdp_data_at().
changeset 2ad413135033 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=2ad413135033
author: enevill
date: Tue Jan 06 16:51:03 2015 +0000
Add java.lang.ref.Reference.get intrinsic to template interpreter
changeset 3552edba94e0 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=3552edba94e0
author: enevill
date: Mon Feb 02 11:29:37 2015 -0800
8072129: [AARCH64] missing fix for 8066900
Summary: add 8066900 fix to arm64 code.
Reviewed-by: kvn
diffstat:
src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp | 4 +-
src/cpu/aarch64/vm/interp_masm_aarch64.cpp | 3 +-
src/cpu/aarch64/vm/stubGenerator_aarch64.cpp | 3 +-
src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp | 73 +++++++++++++++++++++-
4 files changed, 78 insertions(+), 5 deletions(-)
diffs (132 lines):
diff -r 71fa31628126 -r 3552edba94e0 src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp Thu Jan 22 02:55:40 2015 +0000
+++ b/src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp Mon Feb 02 11:29:37 2015 -0800
@@ -377,7 +377,7 @@
case handle_exception_nofpu_id:
case handle_exception_id:
// At this point all registers MAY be live.
- oop_map = save_live_registers(sasm, id == handle_exception_nofpu_id);
+ oop_map = save_live_registers(sasm, id != handle_exception_nofpu_id);
break;
case handle_exception_from_callee_id: {
// At this point all registers except exception oop (r0) and
@@ -441,7 +441,7 @@
case handle_exception_nofpu_id:
case handle_exception_id:
// Restore the registers that were saved at the beginning.
- restore_live_registers(sasm, id == handle_exception_nofpu_id);
+ restore_live_registers(sasm, id != handle_exception_nofpu_id);
break;
case handle_exception_from_callee_id:
// WIN64_ONLY: No need to add frame::arg_reg_save_area_bytes to SP
diff -r 71fa31628126 -r 3552edba94e0 src/cpu/aarch64/vm/interp_masm_aarch64.cpp
--- a/src/cpu/aarch64/vm/interp_masm_aarch64.cpp Thu Jan 22 02:55:40 2015 +0000
+++ b/src/cpu/aarch64/vm/interp_masm_aarch64.cpp Mon Feb 02 11:29:37 2015 -0800
@@ -833,9 +833,10 @@
// jcc(Assembler::negative, L);
// addptr(data, (int32_t) DataLayout::counter_increment);
// so we do this
+ ldr(rscratch1, addr);
subs(rscratch1, rscratch1, (unsigned)DataLayout::counter_increment);
Label L;
- br(Assembler::CS, L); // skip store if counter overflow
+ br(Assembler::LO, L); // skip store if counter underflow
str(rscratch1, addr);
bind(L);
} else {
diff -r 71fa31628126 -r 3552edba94e0 src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
--- a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp Thu Jan 22 02:55:40 2015 +0000
+++ b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp Mon Feb 02 11:29:37 2015 -0800
@@ -316,7 +316,8 @@
#endif
// pass parameters if any
__ mov(esp, sp);
- __ sub(sp, sp, os::vm_page_size()); // Move SP out of the way
+ __ sub(rscratch1, sp, c_rarg6, ext::uxtw, LogBytesPerWord); // Move SP out of the way
+ __ andr(sp, rscratch1, -2 * wordSize);
BLOCK_COMMENT("pass parameters if any");
Label parameters_done;
diff -r 71fa31628126 -r 3552edba94e0 src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp
--- a/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp Thu Jan 22 02:55:40 2015 +0000
+++ b/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp Mon Feb 02 11:29:37 2015 -0800
@@ -673,7 +673,78 @@
// Method entry for java.lang.ref.Reference.get.
address InterpreterGenerator::generate_Reference_get_entry(void) {
- return NULL;
+#if INCLUDE_ALL_GCS
+ // Code: _aload_0, _getfield, _areturn
+ // parameter size = 1
+ //
+ // The code that gets generated by this routine is split into 2 parts:
+ // 1. The "intrinsified" code for G1 (or any SATB based GC),
+ // 2. The slow path - which is an expansion of the regular method entry.
+ //
+ // Notes:-
+ // * In the G1 code we do not check whether we need to block for
+ // a safepoint. If G1 is enabled then we must execute the specialized
+ // code for Reference.get (except when the Reference object is null)
+ // so that we can log the value in the referent field with an SATB
+ // update buffer.
+ // If the code for the getfield template is modified so that the
+ // G1 pre-barrier code is executed when the current method is
+ // Reference.get() then going through the normal method entry
+ // will be fine.
+ // * The G1 code can, however, check the receiver object (the instance
+ // of java.lang.Reference) and jump to the slow path if null. If the
+ // Reference object is null then we obviously cannot fetch the referent
+ // and so we don't need to call the G1 pre-barrier. Thus we can use the
+ // regular method entry code to generate the NPE.
+ //
+ // This code is based on generate_accessor_enty.
+ //
+ // rmethod: Method*
+ // r13: senderSP must preserve for slow path, set SP to it on fast path
+
+ address entry = __ pc();
+
+ const int referent_offset = java_lang_ref_Reference::referent_offset;
+ guarantee(referent_offset > 0, "referent offset not initialized");
+
+ if (UseG1GC) {
+ Label slow_path;
+ const Register local_0 = c_rarg0;
+ // Check if local 0 != NULL
+ // If the receiver is null then it is OK to jump to the slow path.
+ __ ldr(local_0, Address(esp, 0));
+ __ cbz(local_0, slow_path);
+
+
+ // Load the value of the referent field.
+ const Address field_address(local_0, referent_offset);
+ __ load_heap_oop(local_0, field_address);
+
+ // Generate the G1 pre-barrier code to log the value of
+ // the referent field in an SATB buffer.
+ __ enter(); // g1_write may call runtime
+ __ g1_write_barrier_pre(noreg /* obj */,
+ local_0 /* pre_val */,
+ rthread /* thread */,
+ rscratch2 /* tmp */,
+ true /* tosca_live */,
+ true /* expand_call */);
+ __ leave();
+ // areturn
+ __ andr(sp, r13, -16); // done with stack
+ __ ret(lr);
+
+ // generate a vanilla interpreter entry as the slow path
+ __ bind(slow_path);
+ (void) generate_normal_entry(false);
+
+ return entry;
+ }
+#endif // INCLUDE_ALL_GCS
+
+ // If G1 is not enabled then attempt to go through the accessor entry point
+ // Reference.get is an accessor
+ return generate_accessor_entry();
}
/**
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