Request for reviews (S): 6814842: Load shortening optimizations

[Christian Thalinger]

On Mon, 2009-03-09 at 12:09 -0700, John Rose wrote:
> On Mar 9, 2009, at 11:53 AM, Tom Rodriguez wrote:
> 
> >> I see.  Sounds like too much work and possible problems for such a  
> >> small
> >> (probably not very often applied) optimization.  Should I drop it?
> >
> > I think the bang for the buck is low to change it at the ideal  
> > level.  Can't this be addressed in the ad files?  The adds to deal  
> > with endianness will get hidden in the encoding so it won't effect  
> > alias analysis.
> 
> We tried shortening 64- to 32-bit loads once, and we backed off.   
> IIRC, there was an interaction with copy coalescing or some other post- 
> match logic.  I looked in the old teamware histories, but couldn't  
> find evidence of it, so it's just a hazy memory of years ago.
> 
> Load shortening might make sense very late, after register allocation,  
> near post-allocation copy removal.  At that point, you should be able  
> to alter offsets also, so you are not limited just to the word or byte  
> which happens to come first in the CPU's endian order.

Well, to me anything sounds nicer than writing a bunch of AD instructs
for every architecture, as the code boils down to existing instructs
anyway.  Of course I don't know where "that point" is and what I can do
there :-)

-- Christian