Request for reviews (S): 6814842: Load shortening optimizations

Tom Rodriguez Thomas.Rodriguez at Sun.COM
Mon Mar 9 12:56:15 PDT 2009


>> Load shortening might make sense very late, after register  
>> allocation,
>> near post-allocation copy removal.  At that point, you should be able
>> to alter offsets also, so you are not limited just to the word or  
>> byte
>> which happens to come first in the CPU's endian order.
>
> Well, to me anything sounds nicer than writing a bunch of AD instructs
> for every architecture, as the code boils down to existing instructs
> anyway.  Of course I don't know where "that point" is and what I can  
> do
> there :-)

The adlc does tend for more verboseness than I would really like.  If  
there was more uniformity between declarations in our ad files I could  
imagine a shared ad file that would capture some of these special  
matches at a high level and rely either on well known expand rules or  
ins_encodings to do the final code emission though we might run up  
against type problems.

In some cases it would be useful if a single instruct definition could  
include mutiple match rules though in that case you run into issues  
with type mismatches since some might use RegI and others RegL.  If we  
could figure out a syntax for that I don't think it wouldn't be hard  
to implement at the bottom by just making variants of the original  
MachNode the way we do for commutative ops.

Maybe if it were possible to declare instructs without specifying the  
register type and have the type be inferred from the types in the  
match rule we could write that cleanly.  In general it would be good  
if the adlc understood the real types of the nodes in the graph at  
least so it could complain about mismatches. If it could use that to  
find the real operands to use would could write something more  
compact.  Alternatively we could just make up a placeholder syntax for  
it.  Maybe something like:

instruct loadUB(<T> dst, memory mem) %{
   match(Set <rRegI> dst (LoadUB mem));
   match(Set <rRegL> dst (ConvI2L (LoadUB mem)));

   ...
%}

This doesn't help with the load shortening on all platforms since some  
will need extra offsets to deal with endianness but if the encoding  
and format were the same you could use the same thing.

>
>
> -- Christian
>




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