review (S) for 6978249: spill between cpu and fpu registers when those moves are fast

[Vladimir Kozlov]

Tom,

c2_globals.hpp:

+           "Spill integer registers to XMM instead of stack when possible")  \
                                         ^FPU registers

coalesce.cpp:
How it is related to FPU spilling?

matcher.cpp:
this code is x86 specific, for sparc it would be different. Need comment so we will not forget to fix it for sparc.
Why you added spill mask for F/D to I/L? Are these changes allow to spill FPU regs to GPU regs?
Also could you use one #ifdef?

reg_split.cpp:
The next comment does not explain why we need to split for Calls:
// These need a Split regardless of overlap or pressure


On 8/18/10 3:19 PM, Tom Rodriguez wrote:
> http://cr.openjdk.java.net/~never/6978249
>
> 6978249: spill between cpu and fpu registers when those moves are fast
> Reviewed-by:
>
> On some architectures moves between CPU and FPU registers are fast so
> they can be used for spilling instead of the stack.  This change adds
> a new flag UseFPUForSpilling and sets up the spill reg masks to allow
> this when the flag is on.  Currently for Nehalem class chips it seems
> to be a uniform win but we'll keep it under AggressiveOpts for now.
> There are some minor changes to spilling logic that are currently
> guarded until we determine that they are generally a good idea.  I
> also moved the logic for PrintFlagsFinal since the initialization of
> several subsystems may change some flag values which will be missed by
> the current location.  Tested with scimark, ctw and the nsk tests on
> 32 and 64 bit.