RFR(L): 8031321 Support Intel bit manipulation instructions

[Florian Weimer]

On 02/13/2014 11:54 PM, Igor Veresov wrote:
> Can I please get a second review for this?
>
> http://cr.openjdk.java.net/~iveresov/8031321/webrev.04/

Slightly unrelated: I think you can emulate TZCNT on AMD with a MOV and 
a good-old BSF because AMD CPUs do not change the destination operand if 
the input is zero (no conditional branch needed).  LZCNT and BSR are a 
bit further apart, but the conditional branch could be removed there as 
well.

(Obviously, this assumes that the AMD instruction set manual can be 
trusted in this regard. :-)

-- 
Florian Weimer / Red Hat Product Security Team