RFR(L): 8031321 Support Intel bit manipulation instructions

[Igor Veresov]

But you have to return 64 in case when all bits are 0:

instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
  predicate(!UseCountTrailingZerosInstruction);
  match(Set dst (CountTrailingZerosL src));
  effect(KILL cr);

  format %{ "bsfq    $dst, $src\t# count trailing zeros (long)\n\t"
            "jnz     done\n\t"
            "movl    $dst, 64\n"
      "done:" %}
  ins_encode %{
    Register Rdst = $dst$$Register;
    Label done;
    __ bsfq(Rdst, $src$$Register);
    __ jccb(Assembler::notZero, done);
    __ movl(Rdst, BitsPerLong);
    __ bind(done);
  %}
  ins_pipe(ialu_reg);
%}

We could’ve used a conditional move though, but I don’t think modern CPUs care that much.

igor


On Feb 14, 2014, at 2:37 AM, Florian Weimer <fweimer at redhat.com> wrote:

> On 02/13/2014 11:54 PM, Igor Veresov wrote:
>> Can I please get a second review for this?
>> 
>> http://cr.openjdk.java.net/~iveresov/8031321/webrev.04/
> 
> Slightly unrelated: I think you can emulate TZCNT on AMD with a MOV and a good-old BSF because AMD CPUs do not change the destination operand if the input is zero (no conditional branch needed).  LZCNT and BSR are a bit further apart, but the conditional branch could be removed there as well.
> 
> (Obviously, this assumes that the AMD instruction set manual can be trusted in this regard. :-)
> 
> -- 
> Florian Weimer / Red Hat Product Security Team

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