RFR(L): 8031321 Support Intel bit manipulation instructions

[Florian Weimer]

On 02/14/2014 09:27 PM, Igor Veresov wrote:
> But you have to return 64 in case when all bits are 0:
>
> instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
>    predicate(!UseCountTrailingZerosInstruction);
>    match(Set dst (CountTrailingZerosL src));
>    effect(KILL cr);
>
>    format %{ "bsfq    $dst, $src\t# count trailing zeros (long)\n\t"
>              "jnz     done\n\t"
>              "movl    $dst, 64\n"
>        "done:" %}
>    ins_encode %{
>      Register Rdst = $dst$$Register;
>      Label done;
>      __ bsfq(Rdst, $src$$Register);
>      __ jccb(Assembler::notZero, done);
>      __ movl(Rdst, BitsPerLong);
>      __ bind(done);
>    %}
>    ins_pipe(ialu_reg);
> %}

I meant something like this:

instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
   predicate(!UseCountTrailingZerosInstruction);
   match(Set dst (CountTrailingZerosL src));
   effect(KILL cr);

   format %{ "movl    $dst, 64\n"
             "bsfq    $dst, $src\t# count trailing zeros (long)\n\t" %}
   ins_encode %{
     Register Rdst = $dst$$Register;
     __ movl(Rdst, BitsPerLong);
     __ bsfq(Rdst, $src$$Register);
   %}
   ins_pipe(ialu_reg);
%}

And you also need some constraint that src and dst isn't the same.  (Not 
sure how to express that.)

This is based on the following statement in "AMD64 Architecture
Programmer's Manual, Volume 3: General-Purpose and System Instructions", 
as part of the BSF instruction description:

"If the second operand contains 0, the instruction sets ZF to 1 and does 
not change the contents of the destination register."

-- 
Florian Weimer / Red Hat Product Security Team