RFR: aarch64: add support for vectorizing floating-point fabs & fneg

[Andrew Haley]

On 24/09/15 14:22, Felix Yang wrote:
> + #define INSN(NAME, opc, opc2) \
> +  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
>               \
> +    starti;
>               \
> +    assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");
>              \
> +    f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24), f(1, 23);
>              \
> +    f(T==T2D ? 1:0, 22), f(opc2, 21, 10), rf(Vn, 5), rf(Vd, 0);
>               \
> +  }
> +
> +  INSN(fabs, 0, 0b100000111110);
> +  INSN(fneg, 1, 0b100000111110);
> +

FABS and FNEG are instances of the "AdvSIMD two-reg misc" pattern.  Please use it.
Please don't use so much space on the right hand side of continuations lines.

Andrew.