RFR: aarch64: add support for vectorizing floating-point fabs & fneg

[Felix Yang]

On 26 September 2015 at 00:41, Andrew Haley <aph at redhat.com> wrote:

> On 24/09/15 14:22, Felix Yang wrote:
> > + #define INSN(NAME, opc, opc2) \
> > +  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
> >               \
> > +    starti;
> >               \
> > +    assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");
> >              \
> > +    f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24), f(1,
> 23);
> >              \
> > +    f(T==T2D ? 1:0, 22), f(opc2, 21, 10), rf(Vn, 5), rf(Vd, 0);
> >               \
> > +  }
> > +
> > +  INSN(fabs, 0, 0b100000111110);
> > +  INSN(fneg, 1, 0b100000111110);
> > +
>
> FABS and FNEG are instances of the "AdvSIMD two-reg misc" pattern.  Please
> use it.
> Please don't use so much space on the right hand side of continuations
> lines.
>
> Andrew.
>


     OK. I have rewritten this as:

+#define ASSERTION (T == T2S || T == T4S || T == T2D)
+  INSN(fabs, 0, 0b01111);
+  INSN(fneg, 1, 0b01111);
+#undef ASSERTION
+

    Please review the v2 patch:
http://people.linaro.org/~felix.yang/aarch64-fabs-fneg-v2.diff
<http://people.linaro.org/~felix.yang/aarch64-fabs-fneg-v1.diff>
    How about this one?

    Thanks for your help,
Felix.
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