RFR(M): 8154826: AArch64: take better advantage of base + shifted offset addressing mode

[Andrew Haley]

On 27/04/16 10:11, Doerr, Martin wrote:
> Would this be good for aarch64 as well?

On AArch64, LoadConP is

    mov reg, #x
    movk reg, #y shl #16
    movk reg, #z shl 32

(3 cycles latency)

LoadConN + DecodeN heap-based

   mov reg, #x
   movk reg, #y shl #16
   add reg, heapbase, reg shl #3

(4 cycles latency)

Andrew.