RFR(M): 8154826: AArch64: take better advantage of base + shifted offset addressing mode

[Vladimir Kozlov]

Hi Andrew,

Does size of immediate value have affect on latency on aarch64?
For ConP it is 64-bit constant and for ConN it is 32-bit.

Also, as Martin pointed, such constants are loaded from constant table now on SPARC and PPC. What about aarch64?

Thanks,
Vladimir

On 4/27/16 3:07 AM, Andrew Haley wrote:
> On 27/04/16 10:11, Doerr, Martin wrote:
>> Would this be good for aarch64 as well?
>
> On AArch64, LoadConP is
>
>     mov reg, #x
>     movk reg, #y shl #16
>     movk reg, #z shl 32
>
> (3 cycles latency)
>
> LoadConN + DecodeN heap-based
>
>    mov reg, #x
>    movk reg, #y shl #16
>    add reg, heapbase, reg shl #3
>
> (4 cycles latency)
>
> Andrew.
>