[aarch64-port-dev ] RFR: AArch64: incorrect code generation for StoreCM

[Andrew Dinn]

On 03/07/18 10:26, aph wrote:
> On 07/03/2018 09:57 AM, Andrew Dinn wrote:
>> The correct generated sequences should be
>>
>>   str ; dmb ishst ; strb
>>
>> and
>>
>>   dmb ish ; stlr; dmb ishst ; strb ; dmb ish
> 
> What is the leading  DMB ISH  supposed to do here?  The STRB can't move and
> the STLR is enough for a volatile store.
Oops, as if this is not confusing enough ... Sorry, that was explained
all wrong. Let me try again.

For a volatile store with gc config XX:+UseConcMarkSeepGC
-XX:-UseCondCardMark the back end used to generate

  stlr   # when -XX:-UseBarriersForVolatile
  strb

and

  dmb ish   # when -XX:+UseBarriersForVolatile
  str
  dmb ishst
  strb
  dmb ish

for cases -XX:-UseBarriersForVolatile and -XX:+UseBarriersForVolatile,
respectively. The patch corrects the former case to

  stlr   # when -XX:-UseBarriersForVolatile
  dmb ishst
  strb

The latter case is already correct.

Similarly, for a CAS the generated code used to look like

  cmpxchw_acq  # when -XX:-UseBarriersForVolatile
  strb

and

  dmb ish    # when -XX:-UseBarriersForVolatile
  cmpxchw
  dmb ishst
  strb
  dmb ish

where cmpxch_acq uses an ldar to load and store the CASed field value
and cmpxchw uses a plain ldr and str

The patch corrects the former case to

  cmpxch_acq  # when -XX:-UseBarriersForVolatile
  dmb ishst
  strb

The latter case is already correct.

Apologies for muddying already obscure waters.

regards,



Andrew Dinn
-----------
Senior Principal Software Engineer
Red Hat UK Ltd
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