[aarch64-port-dev ] RFR: AArch64: incorrect code generation for StoreCM

[Andrew Dinn]

On 04/07/18 10:55, Zhongwei Yao wrote:
> It looks good to me.

Thanks Zhongwei. I will list you as a reviewer in the patch.

I'm still waiting for an ack from Andrew Haley. Unfortunately, he is
away today so a push will be delayed until tomorrow at the earliest.

>>> I'm thinking whether it is OK to replace "stlr; dmb ishst; strb" with
>>> "stlr; strlb" when we using CMS without conditional card marking.
>>> What do you think?
>> 
>> Yes, that does look better. However, I would prefer to implement that as
>> a separate fix if that is ok. I'd like to have a correct version checked
>> in before we try to implement an optimized version.
>>
> Yeah, agree. 
I looked at this and it should be fairly easy to do, The only tricky
thing is ensuring that the memory operand to the StoreCM rules does not
use an index register, displacement or offset -- releasing store
addressing modes are more restricted than normal stores so the rule
needs an indirect type for the mem operand rather than a generic memory
type.

regards,


Andrew Dinn
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