[aarch64-port-dev ] RFR(S): 8204353 - AARCH64: optimize FPU load and stores in macroAssembler

[Dmitrij Pochepko]

06.06.2018 12:23, Andrew Haley пишет:
> On 06/06/2018 08:59 AM, Andrew Haley wrote:
>> On 06/05/2018 08:46 PM, Dmitrij Pochepko wrote:
>>> webrev: http://cr.openjdk.java.net/~dpochepk/8204353/webrev.01/
>>
>> OK, seems reasonable.
>
> Hold on, no.  I replied too quickly.
>
> 2572 void MacroAssembler::push_call_clobbered_registers() {
> 2573   int step = 4 * wordSize;
> 2574   push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
> 2575   sub(sp, sp, step);
> 2576   mov(rscratch1, -step);
> 2577   // Push v0-v7, v16-v31.
> 2578   for (int i = 31; i>= 4; i -= 4) {
> 2579     if (i <= v7->encoding() || i >= v16->encoding())
> 2580       st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
> 2581           as_FloatRegister(i), T1D, Address(sp, rscratch1));
>
> 2582   }
> 2583   st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
> 2584       as_FloatRegister(3), T1D, Address(sp));
> 2585 }
>
> What is "step" in rscratch1 used for here?  Where do we push the registers?
>
You're probably referring to confusing addressing notation here. I was 
confused originally as well.

According to AARCH64 specification, ld* and st* instructions has 3 
addressing modes:
1) base register, no offset
2) post-index, immediate value
3) post-index, register value
(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802b/LD1_advsimd_sngl_vector.html)

Address class was designed with post-index to be an immediate values, 
so, that is probably why "register post-index" mode for ld/st is using 
regular "register offset" mode, treating it as "register post-index".

My patch is using this "register post-index" mode to have less 
instructions generated. I was a bit confused when first tried to use 
this mode and found such specifics. I had to recheck specific 
instruction generation code to be sure.

Thanks,
Dmitrij