[aarch64-port-dev ] RFR(S): 8204353 - AARCH64: optimize FPU load and stores in macroAssembler

[Andrew Haley]

On 06/06/2018 12:41 PM, Andrew Haley wrote:
> On 06/06/2018 12:16 PM, Dmitrij Pochepko wrote:
>> You're probably referring to confusing addressing notation here. I was 
>> confused originally as well.
>>
>> According to AARCH64 specification, ld* and st* instructions has 3 
>> addressing modes:
>> 1) base register, no offset
>> 2) post-index, immediate value
>> 3) post-index, register value
>> (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802b/LD1_advsimd_sngl_vector.html)
>>
>> Address class was designed with post-index to be an immediate values, 
>> so, that is probably why "register post-index" mode for ld/st is using 
>> regular "register offset" mode, treating it as "register post-index".
>>
>> My patch is using this "register post-index" mode to have less 
>> instructions generated. I was a bit confused when first tried to use 
>> this mode and found such specifics. I had to recheck specific 
>> instruction generation code to be sure.
> 
> Oh no, that is too horrible.  We must fix that before using this
> addressing mode for anything else.

But is it even true?  I just grepped for st1 and I can find no examples
of it being used in that way.  Are there any?  I do see this, which looks
fine:

      st1(Vtmp1, Vtmp2, T16B, post(dst, 32));


-- 
Andrew Haley
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
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