[aarch64-port-dev ] RFR(S): 8204353 - AARCH64: optimize FPU load and stores in macroAssembler

[Dmitrij Pochepko]

On 06.06.2018 15:15, Andrew Haley wrote:
> On 06/06/2018 12:41 PM, Andrew Haley wrote:
>> On 06/06/2018 12:16 PM, Dmitrij Pochepko wrote:
>>> You're probably referring to confusing addressing notation here. I was
>>> confused originally as well.
>>>
>>> According to AARCH64 specification, ld* and st* instructions has 3
>>> addressing modes:
>>> 1) base register, no offset
>>> 2) post-index, immediate value
>>> 3) post-index, register value
>>> (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802b/LD1_advsimd_sngl_vector.html)
>>>
>>> Address class was designed with post-index to be an immediate values,
>>> so, that is probably why "register post-index" mode for ld/st is using
>>> regular "register offset" mode, treating it as "register post-index".
>>>
>>> My patch is using this "register post-index" mode to have less
>>> instructions generated. I was a bit confused when first tried to use
>>> this mode and found such specifics. I had to recheck specific
>>> instruction generation code to be sure.
>> Oh no, that is too horrible.  We must fix that before using this
>> addressing mode for anything else.
> But is it even true?  I just grepped for st1 and I can find no examples
> of it being used in that way.  Are there any?  I do see this, which looks
> fine:
>
>        st1(Vtmp1, Vtmp2, T16B, post(dst, 32));
>
I believe I'm the first one to use ld/st with register post-index 
addressing mode in hotspot.

You can take a look here: 
http://hg.openjdk.java.net/jdk/jdk/file/tip/src/hotspot/cpu/aarch64/assembler_aarch64.hpp#l2068
As you can see, switch by a.getMode() has 3 cases:

1) "base_plus_offset" (expecting only 0 offset. This is for "base 
register, no offset" ld/st addressing mode
2) "post"- this if for immediate post-index mode
3) "base_plus_offset_reg" which is treated further as register 
post-index mode.

I'll create separate issue and patch, which will add new address mode 
(something like: "post_reg"). And final syntax for such mode usage will 
be ... Address(post(<reg1>, <reg2>)), which makes it more readable. 
After that I'll update this fpu ld/st optimization patch accordingly.

How about that?

Thanks,
Dmitrij
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