[14] RFR (L): 8235756: C2: Merge AD instructions for DivV, SqrtV, FmaV, AddReductionV, and MulReductionV nodes

[John Rose]

Whew!  Reviewed.

I did not (a) verify that the reduction code was correct before the change,
nor did I (b) verify that there are no functional changes due to the change,
though I did spot-check.  Please, tell me the various reduction templates
are adequately covered by our tests.

For later, I wish we could handle the reduction cases more mechanically.
We now have hand-maintained reduction trees for each power of two
lane count.  Clearly this could be more mechanized, by writing the
reduction of 2N lanes to N lanes once by hand, and then applying it
lg N times for any particular N.  Obviously, don’t do that now.

— John

> On Dec 11, 2019, at 3:53 AM, Vladimir Ivanov <vladimir.x.ivanov at oracle.com> wrote:
> 
> http://cr.openjdk.java.net/~vlivanov/jbhateja/8235756/webrev.00/all/
> https://bugs.openjdk.java.net/browse/JDK-8235756
> 
> Merge AD instructions for the following vector nodes:
>  - DivVF/DivVD
>  - SqrtVF/SqrtVD
>  - FmaVF/FmaVD
>  - AddReductionV*
>  - MulReductionV*
> 
> Individual patches:
> http://cr.openjdk.java.net/~vlivanov/jbhateja/8235756/webrev.00/individual
> 
> Testing: tier1-4, test run on different CPU flavors (KNL, SKL, etc)
> 
> Contributed-by: Jatin Bhateja <jatin.bhateja at intel.com>
> Reviewed-by: vlivanov, sviswanathan, ?
> 
> Best regards,
> Vladimir Ivanov