RFR: 8216392: Enable cmovP_mem and cmovP_memU instructions

[B. Blaser]

On Thu, 17 Jan 2019 at 10:17, Andrew Haley <aph at redhat.com> wrote:
>
> On 1/16/19 8:46 PM, B. Blaser wrote:
>
> > To answer Andrew Haley, one of the major difference between CISC and
> > RISC is specifically the load/store architecture of the latter which
> > is part of most instructions of the former; I don't see many good
> > reasons to generate RISC-like load/store code using only a subset of
> > instructions and to juggle with registers.
>
> Well, yes, but the question remains: does this change actually help
> anything. And if it does, by how much?

Here it is on intel xeon with 5*10e9 iterations:
* mov+cmov = 10.94s
* cmov = 10.15s

Thoughts?

Thanks,
Bernard

$ cat cmov.c
// $ gcc -S cmov.c
// $ cat cmov.s
// $ gcc cmov.s
// $ time ./a.out

#include<time.h>
#include<stdio.h>

void main() {
    struct timespec start, stop;
    clock_gettime(CLOCK_THREAD_CPUTIME_ID, &start);

    for (long i=0; i<5000000000L; i++) {
        asm ("clc");

        asm ("movq -8(%rbp), %rbx");
        asm ("cmovncq %rbx, %rax");

//        asm ("cmovncq -8(%rbp), %rax");
    }

    clock_gettime(CLOCK_THREAD_CPUTIME_ID, &stop);

    long t = ((long)stop.tv_sec) * 1000000000L + stop.tv_nsec;
    t -= ((long)start.tv_sec) * 1000000000L + start.tv_nsec;

    printf("nsec: %ld\n", t);
}
$ gcc -S cmov.c
$ gcc cmov.s
$ time ./a.out
nsec: 10942890857

real    0m10.951s
user    0m10.941s
sys    0m0.003s
$ cat cmov.c
[...]
    for (long i=0; i<5000000000L; i++) {
        asm ("clc");

//        asm ("movq -8(%rbp), %rbx");
//        asm ("cmovncq %rbx, %rax");

        asm ("cmovncq -8(%rbp), %rax");
    }
[...]
$ gcc -S cmov.c
$ gcc cmov.s
$ time ./a.out
nsec: 10149026430

real    0m10.157s
user    0m10.150s
sys    0m0.001s