RFR(S): 8230591: AArch64: Missing intrinsics for Math.ceil, floor, rint

[Pengfei Li]

Hi Andrew,

> Sure, but the code in "AdvSIMD two-reg misc" can easily be made flexible
> enough to accommodate that. All you have to do aas far as I can see is make
> size a parameter: everything else is the same.
> The important thing is that our assembler should follow the layout and
> classification in that manual as closely as we possibly can.

Thanks for your suggestion. I agree that we should align the layout and classification of the assembler code with ArmARM as closely as we can. But I found just adding one "size" parameter for this is not enough. If it is enough the RBIT instruction shouldn't be oddly encoded before in this category (from _rbit to rbit).

The problem here is that, after adding a "size" parameter for this misc category, the 2 bits in the size field [23:22] may be determined by the parameter "size" or the "SIMD_Arrangement T", or both. And who determines which bit differs instruction by instruction. To solve this problem in my latest webrev [1], I added an additional parameter "tmask" which is a 2-bit mask used accompany with "size" to indicate which bits in [23:22] are determined by the "SIMD_Arrangement T". The bit of "tmask" should be set to 1 if corresponding bit marked as "x" in the ArmARM doc.

With this, we can also encode RBIT normally like other instructions in the misc category.

[1] http://cr.openjdk.java.net/~pli/rfr/8230591/webrev.01/

I ran full jtreg and no new failure is found. How do you think of this?

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Thanks,
Pengfei