RFR: 8255438: [Vector API] More instructs in x86.ad should use legacy mode for code-gen

[Vladimir Ivanov]

On Tue, 27 Oct 2020 23:26:58 GMT, Jie Fu <jiefu at openjdk.org> wrote:

>> Good. Thank you for cleaning this up.
>> Please, someone in Oracle runs Mach5 testing with UseAVX=3.
>
>> Good. Thank you for cleaning this up.
>> Please, someone in Oracle runs Mach5 testing with UseAVX=3.
> 
> Thanks @vnkozlov for your review.
> Hope experts from Intel (@sviswa7 , @jatin-bhateja , etc.) can also take a look at this.
> Thanks.

>From correctness perspective, the fix looks good. 
Xeon Phi CPU family doesn't support BW/DQ extensions.

The only concern I have is that the fix completely disables the usage of the upper bank (16-31) registers for those operands irrespective of whether BW/DQ are present or not. It may lead to performance problems when vector register pressure is high.

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PR: https://git.openjdk.java.net/jdk/pull/874