RFR: 8261142: AArch64: Incorrect instruction encoding when right-shifting vectors with shift amount equals to the element width

[Dong Bo]

On Tue, 9 Feb 2021 07:47:57 GMT, Ningsheng Jian <njian at openjdk.org> wrote:

> If src and dst are the same reg, no need to emit code. 

If we want to do this enhancement, I think we need do it for left shifting and all SVE left/right shifting as well for completeness.

> Or maybe c2 can even be improved to optimize this (sh=0 case) out?

We can add code in `Ideal` to optimize it to ORR, but I'm not sure `orr` performs better than `shift` on other platforms.
Seems we have to created a generic new node to do `vector move` here.

> src/hotspot/cpu/aarch64/aarch64_neon.ad line 5271:
> 
>> 5269:     } else {
>> 5270:       if (sh >= 8) sh = 7;
>> 5271:       __ sshr(as_FloatRegister($dst$$reg), __ T8B,
> 
> I think we should add an assert to make sure 0 is not passed to the assembler.

Agree, I'll do this.

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PR: https://git.openjdk.java.net/jdk/pull/2472