RFR: 8261142: AArch64: Incorrect instruction encoding when right-shifting vectors with shift amount equals to the element width [v2]

[Ningsheng Jian]

On Tue, 9 Feb 2021 08:53:14 GMT, Dong Bo <dongbo at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/aarch64_neon.ad line 5285:
>> 
>>> 5283:   ins_encode %{
>>> 5284:     int sh = (int)$shift$$constant;
>>> 5285:     if (sh == 0) {
>> 
>> If src and dst are the same reg, no need to emit code. Or maybe c2 can even be improved to optimize this (sh=0 case) out?
>
>> If src and dst are the same reg, no need to emit code. 
> 
> If we want to do this enhancement, I think we need do it for left shifting and all SVE left/right shifting as well for completeness.
> 
>> Or maybe c2 can even be improved to optimize this (sh=0 case) out?
> 
> We can add code in `Ideal` to optimize it to ORR, but I'm not sure `orr` performs better than `shift` on other platforms.
> Seems we have to created a generic new node to do `vector move` here.

I think with proper optimization, no move is required. But I agree it's beyond the scope of this patch. I will have a look.

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PR: https://git.openjdk.java.net/jdk/pull/2472