RFR: 8261142: AArch64: Incorrect instruction encoding when right-shifting vectors with shift amount equals to the element width [v2]

[Dong Bo]

On Tue, 9 Feb 2021 09:29:50 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> Dong Bo has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
>
> src/hotspot/cpu/aarch64/aarch64_neon_ad.m4 line 2057:
> 
>> 2055:              as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
>> 2056:     } else {ifelse($4, B,`
>> 2057:       if (sh >= 8) sh = 7;
> 
> I think it would be possible to move some of this logic from the AD file into MacroAssembler, with macros to generate the appropriate instruction based on their arguments. This might be cleaner: the logic here is very hard to follow.

I backed out the modifications of `aarch64_neon.ad` and `aarch64_neon_ad.m4`.
The `shift == 0` case is handled by the assembler now. Verified with the regression tests.

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PR: https://git.openjdk.java.net/jdk/pull/2472