RFR: 8261142: AArch64: Incorrect instruction encoding when right-shifting vectors with shift amount equals to the element width [v2]

[Dong Bo]

On Wed, 10 Feb 2021 02:59:24 GMT, Dong Bo <dongbo at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/aarch64_neon_ad.m4 line 2057:
>> 
>>> 2055:              as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
>>> 2056:     } else {ifelse($4, B,`
>>> 2057:       if (sh >= 8) sh = 7;
>> 
>> I think it would be possible to move some of this logic from the AD file into MacroAssembler, with macros to generate the appropriate instruction based on their arguments. This might be cleaner: the logic here is very hard to follow.
>
> I backed out the modifications of `aarch64_neon.ad` and `aarch64_neon_ad.m4`.
> The `shift == 0` case is handled by the assembler now. Verified with the regression tests.

> I think it would be possible to move some of this logic from the AD file into MacroAssembler, with macros to generate the appropriate instruction based on their arguments. This might be cleaner: the logic here is very hard to follow.

Hi, I moved the logic to the assembler.
The assembler will generate different instructions based on the value of `shift`.
If `shift == 0` and need not to accumulte, generated a `mov`.
If `shift == 0` and need to accumulte, generated an `add`.

Also added tests in `aarch64-asmtest.py` to verify the assembler modifications.

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PR: https://git.openjdk.java.net/jdk/pull/2472