RFR: 8259822: [PPC64] Support the prefixed instruction format added in POWER10

[Kazunori Ogata]

On Thu, 21 Jan 2021 00:28:40 GMT, Corey Ashford <github.com+51754783+CoreyAshford at openjdk.org> wrote:

>> The POWER10 processor, which implements Power ISA 3.1 [1], supports new instruction formats where an instruction takes two 32bit words.  The first word is called prefix, and the instructions with prefix are called prefixed instructions.  With more bits in opcode and operand fields, POWER10 supports larger immediate value in an operand, as well as many new instructions.
>> 
>> This is the first changes to handle prefixed instructions, and this adds support of prefixed addi (= paddi) instruction as an example of prefix usage.  paddi accepts 34bit immediate value, while original addi accepts 16bit value.
>> 
>> [1] https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0
>
> src/hotspot/cpu/ppc/assembler_ppc.hpp line 1112:
> 
>> 1110:   static int inv_bi_field(int x)  { return inv_opp_u_field(x, 15, 11); }
>> 1111: 
>> 1112:   // support to extended opcodes (prefixed instructions) introduced by POWER10
> 
> Should this be "introduced by Power ISA 3.1"?  It would be more correct, but probably inconsistent with other, similar comments.

I'll leave it since other comments that refer to a specific ISA implementation use Power X. (I changed POWER10 to Power 10, though.)

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PR: https://git.openjdk.java.net/jdk/pull/2095