RFR: 8276108: Wrong instruction generation in aarch64 backend

[Andrew Haley]

On Mon, 8 Nov 2021 16:36:49 GMT, Patric Hedlin <phedlin at openjdk.org> wrote:

>> C1 code generation on AArch64 may produce bad LDR/STR immediate offset instructions when the actual operand (datum) size is unknown. This change will alter the code generated for the problematic immediate offset to use the register offset version (requiring additional instructions).
>> 
>> Contributed by Nick Gasson.
>> 
>> Added assert in Address::encode() to emphasise the use of a valid immediate (in base_plus_offset).
>> 
>> Added clarifying comment to Address::offset_ok_for_immed() emphasising favouring of the scaled unsigned 12-bit encoding for aligned offsets.
>
> src/hotspot/cpu/aarch64/assembler_aarch64.hpp line 482:
> 
>> 480:                "must be, was: %ld, %d", _offset, size);
>> 481:         unsigned mask = (1 << size) - 1;
>> 482:         if (_offset < 0 || _offset & mask) {
> 
> Prefer(?): (_offset & mask) != 0

This diff is baffling. What changed?

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PR: https://git.openjdk.java.net/jdk/pull/6212