RFR: 8285711: riscv: RVC: Support disassembler show-bytes option

[Fei Yang]

On Fri, 29 Apr 2022 03:28:17 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/assembler_riscv.hpp line 277:
>> 
>>> 275:   static bool is_compressed_instr(address instr) {
>>> 276:     if (UseRVC && (((uint16_t *)instr)[0] & 0b11) != 0b11) {
>>> 277:       // 16-bit instructions end with 0b00, 0b01, and 0b10
>> 
>> Looks like the comments is not correct here? We are checking the start instead of the end of the instruction encoding here. Suggestion: 
>> "16-bit instruction encoding starts with 0b00, 0b01, and 0b10"
>
> Thank you! The viewpoint might be different -- I was looking at the encoding graph, and it's bits `31 30 ... 3 2 1 0` so I used 'end with'; but 'start with' is also definitely correct because they're bits 0 and 1. So I checked the manual and was wondering if using its words ['lowest two bits'](https://github.com/riscv/riscv-isa-manual/blob/04cc07bccea63f6587371b6c75b228af3e5ebb02/src/intro.tex#L478-L482) might be more official?

That also looks fine for me. Better to mention how the instruction is placemented in memory.

"Instructions are stored in memory as a sequence of 16-bit little-endian parcels, regardless of
memory system endianness. Parcels forming one instruction are stored at increasing halfword
addresses, with the lowest-addressed parcel holding the lowest-numbered bits in the instruction
specification."

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PR: https://git.openjdk.java.net/jdk/pull/8421