RFR: 8285711: riscv: RVC: Support disassembler show-bytes option [v2]

[Xiaolin Zheng]

On Fri, 29 Apr 2022 03:36:25 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Thank you! The viewpoint might be different -- I was looking at the encoding graph, and it's bits `31 30 ... 3 2 1 0` so I used 'end with'; but 'start with' is also definitely correct because they're bits 0 and 1. So I checked the manual and was wondering if using its words ['lowest two bits'](https://github.com/riscv/riscv-isa-manual/blob/04cc07bccea63f6587371b6c75b228af3e5ebb02/src/intro.tex#L478-L482) might be more official?
>
> That also looks fine for me. Better to mention how the instruction is placemented in memory.
> 
> "Instructions are stored in memory as a sequence of 16-bit little-endian parcels, regardless of
> memory system endianness. Parcels forming one instruction are stored at increasing halfword
> addresses, with the lowest-addressed parcel holding the lowest-numbered bits in the instruction
> specification."

Thank you for the suggestion, Felix -- changed, and hope it looks good.

One another thing is the `instructions are stored in memory as a sequence of 16-bit little-endian parcels, regardless of memory system endianness` -- I was wondering if the current `Assembler::emit() -> Assembler::emit_int32()` could match it. Also when loading a 32-bit instruction from the memory - I think maybe the 16-bit parcels should be loaded, considering the 16-bit little-endian order, and be combined into one 32-bit instruction? - I cannot find a big-endian simulator to test that, and feel glad to receive any input.

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PR: https://git.openjdk.java.net/jdk/pull/8421