RFR: 8285711: riscv: RVC: Support disassembler show-bytes option [v2]

[Fei Yang]

On Fri, 29 Apr 2022 03:51:31 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> That also looks fine for me. Better to mention how the instruction is placemented in memory.
>> 
>> "Instructions are stored in memory as a sequence of 16-bit little-endian parcels, regardless of
>> memory system endianness. Parcels forming one instruction are stored at increasing halfword
>> addresses, with the lowest-addressed parcel holding the lowest-numbered bits in the instruction
>> specification."
>
> Thank you for the suggestion, Felix -- changed, and hope it looks good.
> 
> One another thing is the `instructions are stored in memory as a sequence of 16-bit little-endian parcels, regardless of memory system endianness` -- I was wondering if the current `Assembler::emit() -> Assembler::emit_int32()` could match it. Also when loading a 32-bit instruction from the memory - I think maybe the 16-bit parcels should be loaded, considering the 16-bit little-endian order, and be combined into one 32-bit instruction? - I cannot find a big-endian simulator to test that, and feel glad to receive any input.

I don't quite understand what you mean here. But let's discuss that as a separate issue when you have more details.

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PR: https://git.openjdk.java.net/jdk/pull/8421