[jdk18] RFR: 8278267: ARM32: several vector test failures for ASHR [v3]

[Hao Sun]

On Mon, 3 Jan 2022 22:53:57 GMT, Dean Long <dlong at openjdk.org> wrote:

>> Hao Sun has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Make minimal updates to exisiting rules
>>   
>>   1. logical left shift rules
>>   a). add is_var_shift check for vslAA_immI rules.
>>   b). for vslAA_reg rules, remove the matching for URShiftV cases as we
>>   have the separate logical right shift rules now.
>>   
>>   2. logical right shift rules
>>   a). add vsrlAA_reg and vsrlAA_reg_var rules.
>>   b). add is_var_shift check for vsrlAA_immI rules.
>>   
>>   3. arithmetic right shift rules
>>   a). add is_var_shift check for vsraAA_reg rules.
>>   b). add vsraAA_reg_var rules
>>   c). for vsraAA_immI rules, add is_var_shift check and update the match
>>   primitive.
>>   
>>   Code style issues(FIXME and the surrounding space in ins_pipe):
>>   1. for modified rules, keep it as it was
>>   2. for newly added rules, update the style
>
> src/hotspot/cpu/arm/arm.ad line 10999:
> 
>> 10997:     "VNEG.S8 $tmp.D,$shift.D\n\t! neg packed8B"
>> 10998:     "VSHL.U16 $dst.D,$src.D,$tmp.D\t! logical right shift packed4S"
>> 10999:   %}
> 
> This matches what aarch64 is doing, right?  I was hoping there was a way for multiple shift instructions to reuse the same negated value, like we do for vsrcntX.  But it would probably require introducing a new operand type, like vecNegatedRShiftX, or doing the negate in the IR like we do for the mask.

Yes. AArch64 works in the same way.

Agree with you. Performance benefit would be obtained if we can reuse the same negated value.

We may want to prepare another patch to enhance right shifts for aarch64(using is_var_shift() and considering your proposed two solutions).

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PR: https://git.openjdk.java.net/jdk18/pull/41