[jdk18] RFR: 8278267: ARM32: several vector test failures for ASHR [v3]

[Dean Long]

On Tue, 4 Jan 2022 04:31:18 GMT, Hao Sun <haosun at openjdk.org> wrote:

>> src/hotspot/cpu/arm/arm.ad line 10999:
>> 
>>> 10997:     "VNEG.S8 $tmp.D,$shift.D\n\t! neg packed8B"
>>> 10998:     "VSHL.U16 $dst.D,$src.D,$tmp.D\t! logical right shift packed4S"
>>> 10999:   %}
>> 
>> This matches what aarch64 is doing, right?  I was hoping there was a way for multiple shift instructions to reuse the same negated value, like we do for vsrcntX.  But it would probably require introducing a new operand type, like vecNegatedRShiftX, or doing the negate in the IR like we do for the mask.
>
> Yes. AArch64 works in the same way.
> 
> Agree with you. Performance benefit would be obtained if we can reuse the same negated value.
> 
> We may want to prepare another patch to enhance right shifts for aarch64(using is_var_shift() and considering your proposed two solutions).

A separate RFE for that sounds good to me.  Please file one.

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PR: https://git.openjdk.java.net/jdk18/pull/41