RFR: 8282555: Missing memory edge when spilling MoveF2I, MoveD2L etc

[Jatin Bhateja]

On Mon, 21 Mar 2022 11:02:35 GMT, Emanuel Peter <duke at openjdk.java.net> wrote:

> This can lead to reversed scheduling, where we read from a stackSlot before we wrote to it, leading to wrong results.

Scheduler is free to move around instructions without explicit control/memory edges but under all circumstances it should still honor USE-DEF constrain. Following code[1] explicitly connects stack spilled definition to its user if CISC variant of user is available and this input[2] is later replaced by frame pointer[3] when CISC instruction gets created during fixup_spill, this does not disturb the semantics since instruction is still able read correct value from stack address emitted for stackOperands.

This seems to be the root cause of the problem as it disconnects original schedule constraining definition from its user. I think having an extra edge for frame pointer for CISC instructions instead of replacing spill definition edge may guide the scheduler to emit legal schedule. 

[1] https://github.com/openjdk/jdk/blob/master/src/hotspot/share/opto/reg_split.cpp#L254
[2] https://github.com/openjdk/jdk/blob/master/src/hotspot/share/opto/chaitin.cpp#L1707
[3] https://github.com/openjdk/jdk/blob/master/src/hotspot/share/opto/chaitin.cpp#L1726

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PR: https://git.openjdk.java.net/jdk/pull/7889