RFR: 8282555: Missing memory edge when spilling MoveF2I, MoveD2L etc

[Emanuel Peter]

On Wed, 23 Mar 2022 14:57:16 GMT, Emanuel Peter <duke at openjdk.java.net> wrote:

>> I wish I better understood the CISC spilling feature, and why we have special treatment for stack slots.  If you can rewrite the rules using Loads, does that mean we can get rid of all special stackSlot and sReg logic?
>> 
>> Does InstructForm::needs_anti_dependence_check() come into play at all?
>
> @dean-long 
> Of course the question is if we should really remove all this logic and specification in ad files under this bug.
> Maybe we can do something minimal now, and file separate RFEs to:
> 1) remove stackSlot from each platform's ad file -> RFE per platform
> 2) once stackSlot does not occur in any ad file, we should be able to remove the logic from the code
> In this we may have to pay attention if there is a performance regression. Not sure if this could happen in this case, but we'd have to make sure anyway (thanks @TobiHartmann for bringing this up).

> @eme64 , I think adding a precedence edge b/w SPILLED_DEF and CISC instruction after replacing SPILLE_DEFs with FP should add necessary data dependency constraint to enable generating a legal schedule.

@jatin-bhateja Great, let's add such a memory edge! How should I do that?

I have two possible solutions, see above for more details:
1. Add `stackSlotI/L/P/D/F` to `MatchNode::needs_ideal_memory_edge` match list.
2. Edit `x86_64.ad` (and other ad files): use `memory` instead of `stackSlot` for `MoveI2F`.

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PR: https://git.openjdk.java.net/jdk/pull/7889