RFR: 8321001: RISC-V: C2 SignumVF [v2]

[Hamlin Li]

On Mon, 4 Dec 2023 06:52:23 GMT, Vladimir Kempik <vkempik at openjdk.org> wrote:

>> Hamlin Li has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   add v0 to effect
>
> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 1681:
> 
>> 1679: void C2_MacroAssembler::signum_fp_v(VectorRegister dst, BasicType bt, int vlen,
>> 1680:                                     VectorRegister zero, VectorRegister one) {
>> 1681:   vsetvli_helper(bt, vlen);
> 
> Can we have a situation where vlen times sew(bt) won't fit into h/w register ?

No, as UseRVV is only enable when vlenb >= 16, and `match_rule_supported_vector` return false if UseRVV == false.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16925#discussion_r1415657105