RFR: 8300109: RISC-V: Improve code generation for MinI/MaxI nodes

[Dmitry Chuyko]

On Fri, 13 Jan 2023 09:45:01 GMT, Fei Yang <fyang at openjdk.org> wrote:

> As described by the issue, code generation for MinI/MaxI nodes on RISC-V could be improved when one of the source register is the same as the destination register. Also the code could be further simplified when that source register is constant 0 making use of the dedicated zero register of the architecture. This adds new match rules for those cases. 
> 
> Testing:
> - [x] Tier1-3 tested with release build on HiFive Unmatched board.
> - [x] Run non-trivial benchmark workloads (dacapo, specjvm, renaissance, etc) with fastdebug build on HiFive Unmatched board.

src/hotspot/cpu/riscv/riscv.ad line 8706:

> 8704: // avoids loading constant 0 into a source register
> 8705: 
> 8706: instruct minI_reg_zero(iRegINoSp dst, immI0 zero)

As mentioned in https://github.com/openjdk/jdk/pull/11570, unfortunately the order of immediate in MinI/MaxI is not quaranteed, at least it is so in Ideal().

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PR: https://git.openjdk.org/jdk/pull/11988