RFR: 8300247: Harden C1 xchg on AArch64 and PPC [v2]

[Erik Österlund]

> In the C1 xchg operation, AArch64 and PPC don't deal well with the input register and output register being the same. In some new code, that can happen. This change aims at solving that issue.
> 
> As for AArch64, the xchg implementation in the macro assembler already deals well with the input and output register being the same. So we just need to remove an assert. As for the PPC implementation, @TheRealMDoerr has written a variation that uses a temp operand ensuring that they are not the same register.

Erik Österlund has updated the pull request incrementally with one additional commit since the last revision:

  RISC-V fix

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Changes:
  - all: https://git.openjdk.org/jdk/pull/12065/files
  - new: https://git.openjdk.org/jdk/pull/12065/files/b361fe26..a423daf6

Webrevs:
 - full: https://webrevs.openjdk.org/?repo=jdk&pr=12065&range=01
 - incr: https://webrevs.openjdk.org/?repo=jdk&pr=12065&range=00-01

  Stats: 2 lines in 1 file changed: 1 ins; 0 del; 1 mod
  Patch: https://git.openjdk.org/jdk/pull/12065.diff
  Fetch: git fetch https://git.openjdk.org/jdk pull/12065/head:pull/12065

PR: https://git.openjdk.org/jdk/pull/12065