RFR: 8301153: RISC-V: pipeline class for several instructions is not set correctly [v2]

[Yadong Wang]

On Sat, 28 Jan 2023 03:14:51 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Witness that some c2 instructions use the inappropriate ins_pipe, e.g.:
>> 
>> 
>> instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
>> 
>>   match(Set dst (MoveI2F src));
>> 
>>   effect(DEF dst, USE src);
>> 
>>   ins_cost(LOAD_COST);
>> 
>>   format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
>> 
>>   ins_encode %{
>>     __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
>>   %}
>> 
>>   ins_pipe(pipe_class_memory);
>> 
>> %}
>> 
>> 
>> We can use the more accurate pipe_class `fp_load_mem_s` instead.
>> 
>> This PR also fixes the side effect of the flags register for two instructions, we should use/kill a flags register.
>> 
>> Testing:
>> 
>> - [x] Tier1~3 on Unmatched board with release build
>
> Feilong Jiang has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains two additional commits since the last revision:
> 
>  - Merge branch 'openjdk:master' into fix_pipeclass
>  - fix pipe_class

lgtm

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Marked as reviewed by yadongwang (Author).

PR: https://git.openjdk.org/jdk/pull/12219