Integrated: 8301153: RISC-V: pipeline class for several instructions is not set correctly

[Feilong Jiang]

On Thu, 26 Jan 2023 13:47:12 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> Witness that some c2 instructions use the inappropriate ins_pipe, e.g.:
> 
> 
> instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
> 
>   match(Set dst (MoveI2F src));
> 
>   effect(DEF dst, USE src);
> 
>   ins_cost(LOAD_COST);
> 
>   format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
> 
>   ins_encode %{
>     __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
>   %}
> 
>   ins_pipe(pipe_class_memory);
> 
> %}
> 
> 
> We can use the more accurate pipe_class `fp_load_mem_s` instead.
> 
> This PR also fixes the side effect of the flags register for two instructions, we should use/kill a flags register.
> 
> Testing:
> 
> - [x] Tier1~3 on Unmatched board with release build

This pull request has now been integrated.

Changeset: 9cc0171e
Author:    Feilong Jiang <fjiang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.org/jdk/commit/9cc0171ed51eef0deb63fe3a5923bae9cf0f5ff0
Stats:     20 lines in 1 file changed: 1 ins; 0 del; 19 mod

8301153: RISC-V: pipeline class for several instructions is not set correctly

Reviewed-by: fyang, yadongwang

-------------

PR: https://git.openjdk.org/jdk/pull/12219