RFR: 8302906: AArch64: Add SVE backend support for vector unsigned comparison [v3]

[changpeng1997]

On Mon, 13 Mar 2023 10:29:27 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> changpeng1997 has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Refactor part of code in C2 assembler and remove some switch-case stmts.
>
> src/hotspot/cpu/aarch64/assembler_aarch64.hpp line 3218:
> 
>> 3216:     f(1, 21), rf(Vm, 16), f(0b111001, 15, 10), rf(Vn, 5), rf(Vd, 0);
>> 3217:   }
>> 3218: 
> 
> This looks OK, but it's in the wrong place in the file. Look at C4.1 A64 instruction set encoding. These instructions are in the "Advanced SIMD three same" group, so they must appear in assembler_aarch64.hpp in the "Advanced SIMD three same" section.
> This is the "AdvSIMD two-reg misc" section.

Sorry for this error.

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PR: https://git.openjdk.org/jdk/pull/12725