RFR: 8316592: RISC-V: implement poly1305 intrinsic [v3]

[Andrew Haley]

On Wed, 1 Nov 2023 18:48:18 GMT, null <duke at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4546:
>> 
>>> 4544:       // partial products without any risk of needing to propagate a
>>> 4545:       // carry out.
>>> 4546:       wide_mul(U_0, U_0HI, S_0, R_0);  wide_madd(U_0, U_0HI, S_1, RR_1, tmp1, tmp2); wide_madd(U_0, U_0HI, S_2, RR_0, tmp1, tmp2);
>> 
>> I'm not sure why in aarch64 version it's written in this format, but would it be better to have one line for each instruction?
>
> Fixed.

Sorry, I hit send too soon.

In the paper, it's

r0·h0 + 5·2**−130·r1.h3 + 5·2**−130·r2·h2 + 5·2**−130·r3·h1,
r0·h1 +           r1·h0 + 5·2**−130·r2·h3 + 5·2**−130·r3·h2,
r0·h2 +           r1·h1 +           r2·h0 + 5·2**−130·r3·h3,
r0·h3 +           r1·h2 +           r2·h1 +           r3·h0

This is:

r0·s0 + 5·2**−130·r1.s1 + 5·2**−130·r0·s2,
r1·s0 +           r0·s1 + 5·2**−130·r1·s2

... because the paper is using 32-bit multiplications.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16417#discussion_r1380001955