RFR: 8319184: RISC-V: improve MD5 intrinsic [v2]

[Fei Yang]

On Fri, 3 Nov 2023 18:07:18 GMT, Antonios Printezis <tonyp at openjdk.org> wrote:

>> Tweaks to the RISC-V MD5 intrinsic.
>> 
>> * do the loads from the buffer more incrementally instead of all in one go
>> * don't mask off the top 32 bits of a register before an addw instruction, as addw will ignore them anyway
>> * remove the rmask32 register, as the mask is not needed any more (only at the start / end and it's 
>> * cleanup some of the register usage
>
> Antonios Printezis has updated the pull request incrementally with one additional commit since the last revision:
> 
>   changes based on code review

Thanks for the update. Two nits remain.

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3964:

> 3962:                                Register a, Register b, Register c, Register d,
> 3963:                                int k, int s, int t,
> 3964:                                Register rtmp1) {

Could you please rename this into `rtmp` so that it will be more consistent in formal parameter naming convention?

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3984:

> 3982:               Register a, Register b, Register c, Register d,
> 3983:               int k, int s, int t,
> 3984:               Register rtmp1, Register rtmp2) {

Now that we have scratch register `t0` available for use in functions md5_FF/GG/HH/II, we could further remove use of `rtmp2`. Then we might want to let `rtmp1` = `t2` while use `x10`-`x11` for `state0`-`state1`. This will help save use of one callee-saved register. Please consider.

-------------

Changes requested by fyang (Reviewer).

PR Review: https://git.openjdk.org/jdk/pull/16453#pullrequestreview-1714231748
PR Review Comment: https://git.openjdk.org/jdk/pull/16453#discussion_r1382761464
PR Review Comment: https://git.openjdk.org/jdk/pull/16453#discussion_r1382779817