RFR: 8316592: RISC-V: implement poly1305 intrinsic [v7]

[ArsenyBochkarev]

On Mon, 6 Nov 2023 18:35:48 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4578:
>> 
>>> 4576:     __ cad(U_1, U_1, t2, t2); // Add carry to U_1 with carry output to t2
>>> 4577:     __ andi(U_2, U_2, bits2);
>>> 4578:     __ add(U_2, U_2, t2); // Add carry to U_2
>> 
>> What happens if U_2 == 0b11 and t2 == 1? Is it possible?
>> If it's possible, do we need another (and final) reduce?
>
> Maybe there is no chance for this to happen, as in the loop there is already one reducing before quit the loop, the `reduce` here is already the final one?
> I'm not quite sure.

There are two cases here:
1. No loop cycles were performed: the maximum value in `U_2` before the `reduce` is `0b11`, so it is cleared by `srli`;
2. Some loop cycles were performed: it is possible for `U_2 == 0b11` and `t2 == 1` to happen at the end of loop's last `reduce` block, that's correct. However, at the next reduce outside the loop, `U_2` would have `0b100` value which would be cleared to safe `0b1` by `srli`.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16417#discussion_r1385044501