RFR: 8316592: RISC-V: implement poly1305 intrinsic [v8]

[ArsenyBochkarev]

On Tue, 7 Nov 2023 16:22:05 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> ArsenyBochkarev has updated the pull request incrementally with three additional commits since the last revision:
>> 
>>  - Move reduce block to standalone function
>>  - Add different registers assert
>>  - Remove unnecessary registers recycling
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4424:
> 
>> 4422:   // are represented as long[5], with BITS_PER_LIMB = 26.
>> 4423:   // Pack five 26-bit limbs into three 64-bit registers.
>> 4424:   void pack_26(Register dest0, Register dest1, Register dest2, Register src, Register tmp1, Register tmp2) {
> 
> If there only use is in `poly1305` implementation, could you please prefix this methid with `poly1305_`?
> Suggestion:
> 
>   void poly1305_pack_26(Register dest0, Register dest1, Register dest2, Register src, Register tmp1, Register tmp2) {

All done.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16417#discussion_r1387079146