RFR: 8320280: RISC-V: Avoid passing t0 as temp register to MacroAssembler::lightweight_lock/unlock

[Robbin Ehn]

On Fri, 17 Nov 2023 02:32:16 GMT, Gui Cao <gcao at openjdk.org> wrote:

> This is inspired by https://bugs.openjdk.org/browse/JDK-8316880.
> MacroAssembler::lightweight_lock/unlock is non-trivial on linux-riscv64 platform. Passing t0(aka x5) as temporary register to these two assember functions can also be error prone. As a reserved scratch register, t0 is implicitly clobberred by various assembler functions. This fixes the issue by finding and passing a different register, which is similar with https://bugs.openjdk.org/browse/JDK-8316880.
> 
> ### Testing:
> - [x]  Run tier1-3 tests with qemu 8.1.50 (default locking mode) (release)
> - [x]  Run non-trivial benchmark workloads (specjbb2005, dacapo, renaissance) with -XX:LockingMode=2 (fastdebug & release)
> - [x] hotspot:tier4 on hifive unmatched (release)

Hi, thanks, looks good, but if 'temp'/'scratch' is not suppose to be t0, why not assert this in the 'callees' ?

E.g. in C2_MacroAssembler::fast_lock this assert:
assert_different_registers(oop, box, tmp, disp_hdr, t0); needs to updated with tmp3Reg.
Other 'callee' have no asserts.

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PR Review: https://git.openjdk.org/jdk/pull/16703#pullrequestreview-1739130559